Ordering Circuits of Matroids

The cycles of a graph give a natural cyclic ordering to their edge-sets, and these orderings are consistent in that two edges are adjacent in one cycle if and only if they are adjacent in every cycle in which they appear together. An orderable matroid is one whose set of circuits admits such a consistent ordering. In this paper, we consider the question of determining which matroids are orderable. Although we are able to answer this question for non-binary matroids, it remains open for binary matroids. We give examples to provide insight into the potential difficulty of this question in general. We also show that, by requiring that the ordering preserves the three arcs in every theta-graph restriction of a binary matroid $M$, we guarantee that $M$ is orderable if and only if $M$ is graphic.


Introduction
In a graph, the edges of each cycle have an ordering on them. But this is not true for the circuits of a matroid. The goal of this paper is to see to what extent we can distinguish graphic matroids by an ordering condition that mimics the ordering condition on the edges of the cycles of a graph.
A reversible cyclic ordering of a finite set X is an arrangement of the elements of X on the vertices of an n-gon with one element at each vertex. Elements x 1 and x 2 of X are adjacent in the ordering when the corresponding vertices of the n-gon lie on a common edge. Figure 1 shows an example of such an ordering (x 1 x 2 . . . x n ). The same ordering can also be denoted, for example, by (x 3 x 2 x 1 x n . . . x 4 ). Throughout this paper, all orderings are assumed to be reversible cyclic orderings unless stated otherwise.
In a graph, there is an associated ordering on the edge set of each cycle. These orderings have the property that two edges are adjacent in an ordering of a given cycle if and only if they are adjacent in the ordering of every cycle in which the edges appear together.
Unlike the cycles of a graph, the circuits of a matroid are sets without inherent order. We give a matroid M an ordering by imposing an ordering on each of its circuits. Such an ordering of M is consistent if, for every pair {e, f } of distinct elements of E(M) and every pair {C, C ′ } of circuits of M with {e, f } ⊆ C ∩ C ′ , if e and f are adjacent in the ordering of C, then e and f are adjacent in the ordering of C ′ . A matroid is called orderable if it has a consistent ordering.
The notation for matroids in this paper follows [5] with one modification. We call a matroid N a series extension of a matroid M if N can be obtained from M by a (possibly empty) sequence of single-element series extensions; a parallel extension is defined analogously.
The primary goal of this work is characterizing orderable matroids. As noted above, our first examples of orderable matroids are graphic matroids.

Proposition 1. If M is a graphic matroid, then M is orderable.
However, orderability is not enough to distinguish graphic matroids from non-graphic matroids. Our main result specifies all non-binary orderable matroids. The infinitely many such matroids are all built from U 2,n for some n 4 by using two operations, which we now describe.
For a matroid M without coloops, a series extension of M is balanced if, for some integer k exceeding one, each element of M is replaced by k elements in series. We call k the order of the balanced series extension. The second operation is a generalization of the operation of adding an element in parallel to another. A theta-graph is a graph consisting of a pair of distinct vertices and three internally disjoint paths between them. Now, let P be a nonempty subset of a series class of a matroid M. Fix an element t of P , contract P − t, and relabel t as t ′ to obtain M ′ . Let N be the cycle matroid of a theta-graph with series classes {t ′ }, P , and P ′ , where |P ′ | = |P |. Finally, let M ′′ be the 2-sum of M ′ and N with basepoint t ′ . The operation transforming M into M ′′ is called parallel-path addition. The size of this addition is |P |; we call P and P ′ parallel paths of M ′′ , and say that M ′′ is obtained from M by adding P ′ in parallel to P . The following theorem is the main result of the paper. When we come to consider binary orderable matroids, we encounter considerable difficulty. For example, as we show in the next section, F * 7 and M * (K 5 ) are not orderable, yet each has an orderable series extension. In view of this, it is natural to consider additional conditions that one can add to orderability in order to distinguish graphic matroids within binary matroids. The next theorem gives three equivalent such additional conditions. Theorem 3. The following are equivalent for a binary matroid M: (i) M is graphic.
(ii) every minor of M is orderable.
(iii) every series minor of M is orderable.
(iv) every parallel minor of M is orderable.
Although, as noted above, there are orderable binary matroids that are not graphic, we know of no counterexample to the following.

Conjecture 4. A 3-connected orderable binary matroid is graphic.
We have, however, made the following progress.

Theorem 5. A 4-connected regular orderable matroid is graphic.
Another condition one can add to orderability to distinguish graphic matroids within binary matroids involves the theta-graphs in a matroid M, where a theta-graph in M is a restriction of M that is isomorphic to the cycle matroid of a theta-graph. Equivalently, it is a restriction of M that is isomorphic to a series extension of U 1,3 . The series classes of a theta-graph are called its theta-arcs. A subset B of a circuit C is a block if there is a listing b 1 , b 2 , . . . , b k of the elements of B such that b i and b i+1 are adjacent for all i in [k − 1]. A consistent ordering of a matroid M is a theta-ordering if every theta-arc of every theta-graph of M is a block in the ordering; M is theta-orderable if it has a theta-ordering.
Theta-orderability turns out to be equivalent to a concept introduced by Wagner [9]. For distinct circuits C and D of a matroid M, an arc of C is a minimal non-empty subset and k such that {i, j, k} = {1, 2, 3}. In Section 4, we prove the following characterization of theta-orderable binary matroids. The equivalence of (i) and (ii) is Wagner's main result [9].
(i) M is graphic; (ii) M has no set of incompatible arcs; and (iii) M is theta-orderable.
The following characterization of theta-orderable non-binary matroids will also be proved in Section 4.
Theorem 7. Let M be a connected non-binary matroid. Then M is theta-orderable if and only if M is a parallel extension of a balanced series extension of U 2,n for some n 4.
In Section 2, after some preliminaries, we prove Theorem 3. The proof of our main result, Theorem 2, is in Section 3, and Theorem 5 is proved in Section 5.

Preliminaries
Our first proposition collects some basic properties of orderability. These properties will be used frequently and often implicitly. We omit their straightforward proofs.  Next, we note a partial converse to Proposition 1.

Proposition 9.
If M is an orderable binary matroid with a spanning circuit, then M is graphic.
Proof. Let C be a spanning circuit of M and e be an element in C. Fix a consistent ordering of M, and take a standard binary representation of M with respect to the basis C − e. Now construct a graph G beginning with a cycle having edge set C, ordered consistently with the fixed ordering of M. Now, for each element f of E(M) − C, let C f be the fundamental circuit of f with respect to C − e. Because C f − f is a block in the ordering, we may add an edge f to G as a chord of C so that it forms a cycle with edge set C f . The result is a graph whose cycle matroid has ground set E(M), has C − e as a basis, and has the same fundamental circuits with respect to this basis as M. Since M and M(G) are binary, we deduce that M = M(G).
We now note a necessary condition for a matroid to be orderable, along with some consequences of this condition. Proof. Assume to the contrary that M has a consistent ordering. Notice that the ordering of X ∪ f is obtained from that of X ∪ e by replacing f with e. Let a and b be the elements in X that are adjacent to e. Using strong circuit elimination on X ∪ e and X ∪ f , we obtain a circuit C ⊆ X ∪ {e, f } containing e but not a, and another C ′ ⊆ X ∪ {e, f } containing f but not b.
As C is not properly contained in either X ∪ e or X ∪ f , it must contain both e and f . Further, M is simple, so C ∩ X is nonempty. Since a and b are the only elements in X adjacent to e or f , it follows that C = {e, f, b}. By symmetry, C ′ = {e, f, a}.
Circuit elimination applied to C and C ′ now yields a circuit D that does not contain e. Then D ⊆ {a, b, f }. Since |X| 3, it follows that D is a proper subset of X ∪ f , a contradiction.
Corollary 11. Let M be a matroid of rank at least three and X be a circuit-hyperplane of M. If E(M) − X is not a parallel class of M, then the matroid obtained from M by relaxing X is not orderable.
We now prove Theorem 3, whose proof relies on the next lemma and its corollary. The following technical property facilitates the statements of these results. A matroid M has the (e, f, g)-property if (i) M has a circuit containing {e, f, g}; (ii) e, f , and g are distinct; and (iii) M has a circuit D containing f but neither e nor g and, with the exception of at most one d in D, there is a circuit of M containing {e, f, g, d}.
Lemma 13. If a matroid M has the (e, f, g)-property, then f is not adjacent to both e and g in a consistent ordering of M.
Proof. Suppose M has the (e, f, g)-property and f is adjacent to both e and g. Then, in the circuit D of condition (iii), f is adjacent to elements d 1 and Corollary 14. Let C be a circuit of a matroid M. Suppose there is an element c of C so that M has the (e, c, g)-property for every choice of e and g in C − c. Then M does not have a consistent ordering.
Proof of Theorem 3. Since graphic matroids are orderable and the class of graphic matroids is minor-closed, (i) implies (ii)-(iv). Let S be the set By results of Tutte [8] and Bixby [1,2], S contains all binary matroids that are excluded minors, excluded series minors, or excluded parallel minors for the class of graphic matroids. Thus we can prove that (i) follows from each of (ii)-(iv) by showing that none of the matroids in S is orderable. Let F 7 be labelled as in Figure 2. Using the element 1 in the circuit {1, 2, 3, 4}, Corollary 14 gives that F 7 has no consistent ordering.
We conclude this section with a pair of examples that indicate the potential difficulty of characterizing orderable binary matroids.
Example 15. This example describes a 12-element orderable series extension of F * 7 , which we refer to as O 1 . Thus, the pair O 1 and F * 7 demonstrates that the class of binary orderable matroids is not closed under the taking of series minors. Let F * 7 be labelled as in Figure 3. We obtain O 1 by adding 1 ′ , 2 ′ , and 7 ′ in series with 1, 2, and 7, respectively, and adding 4 ′ and 4 ′′ in series with 4. Figure 10 gives a consistent ordering of the circuits of O 1 .
Example 16. Let K 5 be labelled as in Figure 4. We obtain a regular, non-graphic matroid O 2 from M * (K 5 ) by adding elements 0 ′ and 2 ′ in series with 0 and 2, respectively. Figure 11 gives a consistent ordering of O 2 .

A Characterization of Non-Binary Orderable Matroids
In this section, we prove Theorem 2. We begin by finding the orderable series extensions of uniform matroids and their consistent orderings. These results allow us to characterize the non-binary orderable matroids that are 3-connected, from which we obtain the full characterization using the canonical tree decomposition of Cunningham and Edmonds [3].
A uniform matroid is binary if and only if it is graphic. Thus, the binary uniform matroids are certainly orderable, as are those whose rank is at most two. Proposition 10 implies this list is complete.

Corollary 17. A uniform matroid is orderable if and only if it is binary or has rank at most two.
The next two results deduce the structure of a consistent ordering of a series extension of a non-binary uniform matroid, and show that such an ordering can be used to consistently order the underlying uniform matroid. For a non-coloop element e of a matroid M, we denote the series class of M containing e by S e or sometimes by S e (M).
Let M be a matroid with a consistent ordering. Suppose X and Y are disjoint subsets of a circuit C of M. We say X and Y are adjacent if there is an adjacent pair of elements x and y, where x belongs to X and y belongs to Y . Let B be the union of a set of blocks that belong to a common circuit of M. If there is a listing B 1 , B 2 , . . . , B k of the blocks in B such that B i and B i+1 are adjacent for all i in [k − 1], then B is a section. Finally, let S be a series class of M. If a block of M is contained in S and is maximal with this property, then it is called an S-block.
Lemma 18. Let M be an orderable series extension of a non-binary uniform matroid U r,n and fix a consistent ordering of M. Let C be a circuit of M, and let x and y be elements of C from distinct series classes of M.
(i) If a section K in C is adjacent to a pair of S x -blocks, then K must contain an S y -block.
(ii) Every series class S of M has the same number of S-blocks.
Proof. For (i), suppose to the contrary that there is a section K in C that contains no S yblock and is adjacent to a pair of distinct S x -blocks. As M is non-binary, 2 r n−2 and there is a circuit D x of M that contains K and S x but avoids S y . Let D y = (D x −S x ) ∪S y . Observe that, since M is a series extension of U r,n , the set D y is a circuit. The consistency of D y with C implies that K is not adjacent to S y -blocks in D y , but the consistency of D y with D x gives that K can only be adjacent to S y -blocks in D y , a contradiction. We now deduce (ii) from (i). Let S be a series class of E(M) for which the number of S-blocks is as large as possible. We may assume this number exceeds one. In a circuit C containing S, let K be a minimal section that is adjacent to a pair of distinct S-blocks. Note that the number of such minimal sections in C equals the number of S-blocks. Let S ′ be a series class of M contained in C that is distinct from S. Part (i) implies there is an S ′ -block in K and, as K contains no S-blocks, (i) further implies that there is exactly one S ′ -block in K. Thus there are the same number of S ′ -blocks as S-blocks. Part (ii) now follows.
Proposition 19. Let U r,n be a non-binary uniform matroid. If a series extension of U r,n is orderable, then so is U r,n . Figure 12: The circuit C in the proof of Proposition 19.
Proof. Let M be an orderable series extension of U r,n and fix a consistent ordering of M. By Lemma 18(ii), there is an integer k 1 such that every series class of M is divided into exactly k blocks. If k = 1, the result follows immediately, so assume k 2.
Let [n] be the ground set of U r,n . Consider the circuit C of M that contains the set {1, 2, . . . , r + 1}. Label the S 1 -blocks in C as B 1 , B 2 , . . . , B k , such that B i and B i+1 abut a section K i that does not contain S 1 -blocks, as in Figure 12.
Applying Lemma 18(i), we see that each section K i contains exactly one S j -block for all j in {2, 3, . . . , r + 1}. Thus, B i ∪ K i defines a permutation of {1, 2, . . . , r + 1} that begins with 1. We show this permutation is the same for all i.
Without loss of generality, suppose the block in K 1 adjacent to B 1 is an S 2 -block. If the block in K 2 adjacent to B 2 is an S j -block with j = 2, then the S j -blocks in K 1 and K 2 abut a section that contains no S 2 -block, contradicting Lemma 18(i). Thus the block in K 2 adjacent to B 2 is an S 2 -block. Repeating this argument gives that B 1 ∪ K 1 and B 2 ∪ K 2 define the same permutation on {1, 2, . . . , r + 1}. It follows that B i ∪ K i defines the same permutation on {1, 2, . . . , r + 1} for all i in [n]. Thus B i ∪ K i ∪ B i+1 defines the same reversible cyclic ordering on {1, 2, . . . , r + 1} for all i in [n]; it is this reversible cyclic ordering that we extract from C and use to order the circuit {1, 2, . . . , r + 1} in U r,n .
In this way, every circuit of U r,n is ordered using the corresponding circuit of M. Since the ordering of M is consistent, so too is the ordering it gives to U r,n .
Theorem 20. Let U r,n be a non-binary uniform matroid of rank at least three. If M is a matroid with a series minor isomorphic to U r,n , then M is not orderable.
Proof. By [5, Proposition 5.4.2], we may write U r,n = M\X/Y where each element of Y is in series with an element of M\X not in Y . By Corollary 17, the matroid U r,n is not orderable. Therefore, by Proposition 19, neither is its series extension M\X. Thus, M is not orderable.
Recall that, in a balanced series extension N of a matroid M without coloops, each element of M is replaced by k elements in series for some positive integer k.
Lemma 21. Let N be a balanced series extension of U 2,n for some n 4. Then N is orderable.
Proof. Let [n] be the ground set of U 2,n . For each x in E(U 2,n ), let {x 0 , x 1 , . . . , x k−1 } be the series class S x of N that corresponds to x. Subscript arithmetic will be done modulo k. Let C 1 be the set of circuits of N containing S 1 . For the circuit C = S 1 ∪ S x ∪ S y in C 1 with x < y, give C the ordering To see that the circuits in C 1 are consistent, suppose e and f belong to common circuits in C 1 . Then at least one of e and f , say e, is in S 1 . If f is in S 1 , then e and f are never adjacent. Otherwise, f is in S z for some z > 1, so e = 1 s and f = z t for some s and t. If s = t, then e and f are always adjacent; if s = t, then e and f are never adjacent. Now let C 2 be the set of circuits of N not containing S 1 . For the circuit Note that x i is always adjacent to y i+1 and z i+1 . Further, the blocks z i x i−1 y i are ordered so that y i is always adjacent to z i+1 . Thus, the circuits in C 2 are consistent with those in C 1 .
Finally, the circuits in C 2 are consistent. Suppose instead that there are circuits C and D in C 2 and elements x s and y t in C ∩ D so that x s and y t are adjacent in C but not in D. Assume x < y. From C, we have that t = s + 1, but, from D, we have that t = s + 1, a contradiction.
The following proposition specializes some of the results about uniform matroids to U 2,n with n 4. These rank-two uniform matroids will serve as the foundation from which all non-binary orderable matroids are built. Proof. Statement (ii) follows from combining (i) with Lemma 18(ii), so it suffices to show (i). Let E(U 2,n ) = [n]. Suppose, to the contrary, that M has an S 1 -block B of size at least two. Applying Lemma 18(i), we have that B is adjacent to both an S 2 -block and an S 3block in the circuit of M containing {1, 2, 3}. Let 1 2 be the element of B adjacent to the S 2 -block and let 1 3 be the element of B adjacent to the S 3 -block, where 1 2 and 1 3 are necessarily distinct. In the circuit of M containing {1, 2, 4}, Lemma 18(i) now gives that B is adjacent to both an S 2 -block and an S 4 -block. Consistency dictates that 1 2 is again adjacent to the S 2 -block. Therefore 1 3 is now adjacent to the S 4 -block.
Now consider the circuit of M containing {1, 3, 4}. Consistency with the two aforementioned circuits requires that 1 3 be adjacent to both an S 3 -block and an S 4 -block. As |B| 2, this is a contradiction.
The next theorem identifies all orderable matroids that are 3-connected and nonbinary.
Theorem 23. If M is a 3-connected non-binary orderable matroid, then M ∼ = U 2,n for some n 4.
The next two results will be used in the proof of this theorem.
Proposition 24. If M is an orderable matroid, then M has no minor isomorphic to U 3,5 .
Proof. Assume instead that M\X/Y ∼ = U 3,5 , with X coindependent and Y independent. Then M * /X\Y ∼ = U 2,5 where M * /X has rank two. Thus, after deleting a set Z of loops from M * /X, we obtain a parallel extension of U 2,n for some n 5. This makes M\(X ∪Z) an orderable series extension of U n−2,n , contradicting Theorem 20.
Proposition 25. If M is an orderable matroid, then M has no minor isomorphic to W 3 .
The proof of this proposition will rely on the next lemma and its corollary. This second pair of results will use the following modification of the (e, f, g)-property. Note that e and g may be equal in this definition.  To see this, first note that, as N * is orderable, it has no U 3,5 -minor by Proposition 24. Thus, si(N) has no U 2,5 -minor. As si(N) is 3-connected and its rank and corank each exceed two, [5, Proposition 12.2.15] gives that si(N) has no U 3,5 -minor. The rank of F * 7 exceeds three, so si(N) also has no F * 7 -minor. Finally, suppose si(N) has an F 7 -minor. Then si(N)|Z ∼ = F 7 for some set Z. As F 7 has no W 3 -minor, si(N) has an element e not in Z. Then si(N)/e has a U 2,5 -restriction, a contradiction. We conclude that si(N) has no F 7 -minor. Thus 27.1 holds.
By 27.1, si(N) has the form P G(2, 3) − K, where K is a restriction of O 7 , the complement of W 3 in P G(2, 3). The matroid O 7 is obtained from M(K 4 ) by adding a point freely to an existing 3-point line; the fifteen restrictions of O 7 are given in Figure 13. In the remainder of the proof, we eliminate each possibility for K.
If K = U 0,0 , then si(N) = P G(2, 3). Let si(N) be labelled as in Figure 14. Suppose N * has a consistent ordering, and let B x , B y , and B z be S x -, S y -, and S z -blocks in a common circuit C of N * , where x, y, and z are elements of E(si(N)). Assume also that B y is adjacent to B x and B z . Then, by Lemma 26, co(N * ) does not have the series (x, y, z)-property. We show next that 27.2. x, y, and z are collinear in si(N), and x = z.
Suppose x, y, and z are not collinear in si(N). Then one easily finds circuits of co(N * ) that verify the series (x, y, z)-property in co(N * ), a contradiction. Similarly, when x = z there are circuits of co(N * ) that verify the series (x, y, z)-property in co(N * ), a contradiction. Thus, 27.2 holds. By symmetry, we may assume that C is the circuit {1, 2, 3, 4, 5, 6, 7, 8, 9} of co(N * ); let C ′ be the corresponding circuit of N * . Consider an S 1 -block B in C ′ . The block B is adjacent to an S e -and S f -block for some e and f in C − 1. By 27.2, the elements 1, e, and f are collinear in si(N); without loss of generality, say e = 2 and f = 3. Let B 3 be the S 3 -block adjacent to B. By repeatedly applying 27.2, we have that B 3 is adjacent to an S 2 -block B 2 , the block B 2 is adjacent to another S 1 -block B 1 , the block B 1 is adjacent to another S 3 -block, and so on. It follows that C ′ has a proper subset X of elements not adjacent to any element of C ′ − X, a contradiction.
We conclude that exactly one-third of the elements of E(N) lie on the line {a, b, c}. By symmetry, the same is true of the lines {1, 6, 8}, {3, 5, 7}, and {2, 4, 9}, so now four disjoint lines each account for one-third of the elements in N, a contradiction.
If K = U 2,3 , then si(N) = P G(2, 3)\{b, c, d}. The following equations are obtained by applying Proposition 22(ii) in the minors N/ cl({1}), N/ cl({2}), and N/ cl({3}), respectively: Solving equations (1) and (2) for |E(N)|, we see that For the next six cases, we continue to view N as a parallel extension of a restriction of P G(2, 3), with P G(2, 3) labelled as in Figure 14. However, we now represent the deletion of an element e from P G(2, 3) by setting p e to be 0. Each of these cases is eliminated using the following assertion. Then N * is not orderable. To see this, we first use the minors N/ cl({a}) and N/ cl({b}) to establish the equations p a = p 2 + p 6 + p 7 = p 1 + p 5 + p 9 = p 3 + p 4 + p 8 , from which we obtain 3p a = p 1 + p 2 + · · · + p 9 = 3p b , so p a = p b , and |E(N)| = 5p a . Now, N/ cl({1}) gives that |E(N)| − p 1 = 4(p 2 + p 3 + p a ), and substituting 5p a for |E(N)| produces Finally, since p a = p 1 + p 2 + p 3 , we deduce that p 2 + p 3 = 0, a contradiction. Thus 27.3 holds. The six options for K eliminated by 27.3 are the matroids U 2,2 , U 3,3 , U 3,4 , U 2,3 ⊕ U 1,1 , P (U 2,3 , U 2,3 ), and U 2,3 ⊕ 2 U 2,4 . It is straightforward to check that, for each K in this list, we may set classes of P G(2, 3) equal to zero in such a way that the zeroed classes form a restriction isomorphic to K, and the conditions of 27.3 hold. For example, U 2,3 ⊕ 2 U 2,4 is produced when p 5 , p 7 , p 9 , p c , and p d are the zeroed classes.
Suppose B is adjacent to an S e -block for some e in {2, 4, 6}. Then the consistency of the circuits in X implies that B is adjacent to an S e -block for every e in {2, 4, 6}. The circuits in Y now imply that B is adjacent to an S 2 -, S 4 -, and S 6 -block. Further, B is not adjacent to an S e -block for any e in {3, 5, 7}. It follows that, in the circuit of N * corresponding to {1, 2, 3, 5, 7}, the block B must be adjacent to a pair of S 2 -blocks, contradicting the fact that B is adjacent to both an S 2 -block and an S 4 -block in the circuit of N * corresponding to {1, 2, 3, 4}.
We now know that, for each e in {2, 4, 6}, the block B is not adjacent to an S e -block. The circuits in Y now imply that, in the circuit of N * corresponding to {1, 2, 3, 5, 7}, the block B is adjacent to an S e -block for every e in {3, 5, 7}. This contradiction implies N * is not orderable.
The next proposition is a result of Oxley [4] (see also [5,Corollary 12.2.18]). We will use it to prove Theorem 23.
Proposition 28. A 3-connected non-binary matroid whose rank and corank exceed two has a minor isomorphic to one of W 3 , P 6 , Q 6 , and U 3,6 .
Proof of Theorem 23. Assume that the theorem fails for M. Then r(M) 3. As P 6 , Q 6 , and U 3,6 each have U 3,5 as a minor, Proposition 28 and Propositions 24 and 25 now imply that r * (M) 2, so r * (M) = 2. As M is 3-connected, it follows that M ∼ = U n−2,n for some n 5. Hence M has a U 3,5 -minor, a contradiction.
If In this case, the elements {e 1 , e 2 , . . . , e n−1 } are the edge labels of T . The next theorem of Cunningham and Edmonds [3] (see also [5,Theorem 8.3.10]) tells us that M has a canonical tree decomposition, unique to within relabelling of the edges.
Theorem 29. Let M be a 2-connected matroid. Then M has a tree decomposition T in which every vertex label is 3-connected, a circuit, or a cocircuit, and there are no two adjacent vertices that are both labelled by circuits or are both labelled by cocircuits. Moreover, T is unique to within relabelling of its edges. In the next four lemmas, M is assumed to be a connected, orderable, non-binary matroid whose canonical tree decomposition is T .
Lemma 30. Suppose that T has a vertex label U that is isomorphic to U 2,n for some Proof. We may assume that M is not a parallel extension of U 2,n otherwise (i) holds. For each element y of E(U) that labels an edge of T , let C y be a circuit of M ′ y,U that contains y. As M is not a parallel extension of U 2,n , we may assume that |C x | 3 for some element x. Let M ′′ be the matroid that is obtained from U by attaching each C y via 2-sum. This matroid is a restriction of M having C x − x as a non-trivial series class. Moreover, M ′′ is a series extension of U 2,n and it is orderable. Thus, by Proposition 22(ii), M ′′ is a balanced series extension of U 2,n . Hence (i) holds. Furthermore, |C x | = |C y | 3 for all y in E(U) − {x}. Parts (ii) and (iii) now follow without difficulty.
The next lemma generalizes Lemma 30(ii) to arbitrary edges of T .
Lemma 31. Suppose that T has a vertex label U that is isomorphic to U 2,n for some n 4, and suppose e is an edge label of T . Then the circuits of M ′ e,U that contain e all have the same size.
Proof. Let N be the endpoint of e in the same component of T \e as U. If U = N, then the assertion holds by Lemma 30(ii), so assume otherwise. Let f be the label of the edge incident with U that lies on the path connecting U to N in T . Next, let T ′ be the subtree of T \{e, f } containing N, and let M ′ be the matroid with tree decomposition T ′ .
Fix a circuit C of M ′ that contains e and f . Observe that, for each circuit D of M ′ e,N that contains e, there is a circuit (D − e) ∪ (C − e) of M ′ f,U that contains f . By Lemma 30(ii), the quantity |(D − e) ∪ (C − e)| is the same for each choice of D, so every such circuit D has the same size.
Lemma 32. The tree T has exactly one 3-connected non-binary vertex label, and this label is isomorphic to U 2,n for some n 4.
Proof. As M is non-binary, it has at least one 3-connected non-binary vertex label N. For each element y of E(N) that labels an edge of T , let C y be a circuit of M ′ y,N that contains y. Let M ′′ be the matroid that is obtained from N by attaching each C y via 2-sum. Then M ′′ is a restriction of M. Thus M ′′ is an orderable series extension of N. By Propositions 24, 25, and 28, N ∼ = U 2,n for some n 4. Now suppose T has a pair of 3-connected non-binary vertex labels N 1 ∼ = U 2,n 1 and N 2 ∼ = U 2,n 2 with n 1 , n 2 4. Let e 1 and e 2 be the edge labels of T incident with N 1 and N 2 that lie on the path connecting N 1 and N 2 in T .
By Lemma 30(ii), the circuits of M ′ e 1 ,N 1 containing e 1 all have size k and the circuits of M ′ e 2 ,N 2 containing e 2 all have size ℓ, where k and ℓ are integers exceeding one. Let {e 1 , x, y} be a circuit of N 1 . By Lemma 30(i), x and y are also edge labels of T ; let C x be a circuit of M ′ x,N 1 containing x, and C y be a circuit of M ′ y,N 1 containing y. Then k = |C x | = |C y | by Lemma 30(iii). Now there is a circuit of M ′ e 2 ,N 2 containing e 2 that also contains C x − x and C y − y. Thus, ℓ 2(k − 1) + 1. A symmetric argument gives that k 2(ℓ − 1) + 1, and substitution yields that k 1, a contradiction.
The next lemma rules out 3-connected binary vertex labels that are not circuits or cocircuits. It uses the following result of Seymour [6]. Proof. Suppose B is such a vertex label of T , let U be the unique vertex label with U ∼ = U 2,n and n 4 given by Lemma 32, and say E(U) = {e 1 , e 2 , . . . , e n }. Let p ∈ E(B) and e 1 ∈ E(U) be the labels of the edges incident with B and U, respectively, that lie on the path connecting B to U in T . By Proposition 33, B has a minor isomorphic to M(K 4 ) that uses p.
This minor can be written in the form B/I\I * , where I is independent in B and I * is coindependent in B. This makes B/I a rank-three binary matroid with M(K 4 ) as a restriction, so after deleting the loops from B/I, we obtain a parallel extension of either M(K 4 ) or F 7 . Dually, after deleting the coloops from B\I * , we obtain a series extension of M(K 4 ) or F * 7 . Thus B has a restriction N 1 using p that is a series extension of M(K 4 ) or F * 7 . that contains q. Form the matroid N 2 from N 1 by replacing q with C q − q in E(N 1 ) for each q in E(N 1 ) − p that is an edge label of T . Then N 2 is a series extension of M(K 4 ) or F * 7 that appears as a restriction of M p,B . Now, for each i in {2, 3}, let C e i be a circuit of M ′ e i ,U that contains e i . Then M ′ p,B has a circuit C p that contains p and both C e 2 − e 2 and C e 3 − e 3 . Form the matroid N from N 2 by taking the 2-sum of N 2 and C p across the basepoint p. Then N is a restriction of M that is a series extension of M(K 4 ) or F * 7 . For each element x of M(K 4 ) or F * 7 , let S x be S x (N). By Lemma 31, every circuit of N 2 that contains p has the same size.
Suppose first that N is a series extension of M(K 4 ) with K 4 labelled as in Figure 17. Thus, every circuit of N that contains S p has the same size. Since all circuits of N containing S p have the same size, Similarly, Equations (3) and (4) imply that |S b | = 0, a contradiction. Now suppose that N is a series extension of F * 7 with F * 7 labelled as in Figure 18. Since the circuits of N containing S p must have the same size, Together, these equations imply that Fix a consistent ordering of M. This induces a consistent ordering of N. Consider the circuit C = S p ∪ S 2 ∪ S 3 ∪ S 4 of N. Notice that M has, as a restriction, a series extension U ′ of U 2,n whose ground set contains C. Specifically, Let t be an arbitrary member of the series class S 2 of N. In U ′ , the element t belongs to the class S e 1 , so {t} is an S e 1 -block in the ordering of C by Proposition 22(i). Lemma 18(i) implies that t is adjacent to some element x ∈ S e 2 and some y ∈ S e 3 ; notice that, in N, the elements x and y both belong to S p . Thus, every element of S 2 is adjacent to a pair of elements from S p in C. In particular, t is not adjacent to any element of S 2 or of S 3 . Now observe that t is adjacent to this same pair {x, y} in the circuit S p ∪ S 2 ∪ S 5 ∪ S 6 of N, so t is also not adjacent to any element of S 6 . It follows that t is adjacent to a pair of elements from S 7 in the circuit S 2 ∪ S 3 ∪ S 6 ∪ S 7 of N. Therefore |S 2 | < |S 7 |, contradicting (5). Proof. In forming M ′′ from M, let P ′ be added in parallel to P . As M ′′ has M as a restriction, M is orderable if M ′′ is. Conversely, fix a consistent ordering of M and let C ′′ be a circuit of M ′′ . If C ′′ does not meet P ′ , give C ′′ the same ordering in M ′′ that it has in M. Otherwise, C ′′ contains P ′ and either C ′′ = P ∪ P ′ , or there is a circuit C of M such that C = (C ′′ − P ′ ) ∪ P . In the the latter case, give C ′′ the same ordering in M ′′ that C has in M by replacing every element p ∈ P by the corresponding element p ′ ∈ P ′ .
If C ′′ = P ∪ P ′′ , take a circuit D of M containing P . Let B 1 , B 2 , . . . , B k be the P -blocks of D, numbered sequentially as they appear in a traversal of the ordering of D in M. Proof. Part (i) is immediate. For part (ii), let P 1 be the k-element set that is added in parallel to the subset P 2 of a series class at step s 1 . After the balanced series extension in step s 2 is performed, P 1 and P 2 become parallel paths P ′ 1 and P ′ 2 of size mk. Thus, the same result is obtained by first performing a balanced series extension of order m, then adding the mk-element set P ′ 1 in parallel to the subset P ′ 2 of a series class. We are now ready to prove the main result of the paper, which was given as Theorem 2 in the introduction and is restated here for convenience. Proof. Let n be an integer exceeding three, and let M be a matroid obtained from U 2,n by a sequence of balanced series extensions and parallel-path additions. Lemma 36 implies that M may be obtained from a balanced series extension of U 2,n by a sequence of parallelpath additions, so, by Lemmas 21 and 35, M is orderable.
For the converse, we may assume that M is simple, as adding an element in parallel is a parallel-path addition of size one. If M ∼ = U 2,n , the result holds, so assume otherwise. Let T be the canonical tree decomposition of M. Lemmas 32 and 34 imply that there is a single vertex label U of T for which U ∼ = U 2,n and n 4, and every vertex of T − U is labelled by a circuit or a cocircuit. By Lemma 30(i), each e in E(U) labels an edge of T . Let T ′ e be the component of T \e that does not have U as a vertex. As M is simple, the leaves of T are labelled by circuits. Therefore, if every T ′ e has only one vertex, then M is a series extension of U 2,n , and the result holds by Proposition 22(ii). We show that, if this is not the case, then each T ′ e can be reduced to a single vertex labelled by a circuit via a sequence of deletions that can be undone by parallel-path additions.
Suppose T ′ e has at least two vertices. Since only one vertex of T ′ e is adjacent to U, not all vertices of T ′ e are leaves of T . We now observe that 37.1. T ′ e has a vertex v that (i) is adjacent to a leaf of T ; and (ii) has exactly one neighbor that is not a leaf of T If L is the set of leaves of T , such a vertex v can be found as a leaf of T − L. Since the leaves of T are labelled by circuits and T is canonical, v is labelled by a cocircuit C * . Lemma 31 now implies that the circuits that label the leaves of T adjacent to C * all have the same size, and every element of C * must be used as a basepoint labelling an edge of T .
We can delete all but one of the leaves, C say, of T that are adjacent to C * , along with the corresponding basepoints in C * , since the circuit that labels each deleted leaf can be added via a parallel-path addition. As C * is now a pair of parallel elements, we can delete the leaf labelled C and relabel v with C. At this point, v is a leaf, and is either adjacent to U, in which case the work on this subtree is complete, or v is adjacent to another vertex of T ′ e labelled by a circuit C ′ . In the latter case, keep T canonical by contracting the edge of T between v and C ′ and labelling the resulting vertex with the circuit that is the 2-sum of C and C ′ .
Provided the modification of T ′ e continues to have at least two vertices, condition 37.1 continues to hold, and the process described in the previous paragraph can be repeated. Thus, we may assume T ′ e consists of a single vertex labelled by a circuit. By applying this pruning process on the other subtrees attached to U, the tree T is reduced to the decomposition tree of a balanced series extension of U 2,n . Thus, M can be obtained from a balanced series extension of U 2,n by a sequence of parallel-path additions.

Theta-Orderability
Recall that theta-orderability of a matroid requires a consistent ordering of the matroid with respect to the theta-graphs of that matroid. Each of the elementary properties of orderability given in Proposition 8 also holds for theta-orderability. Their straightforward proofs are omitted.  Next we prove Theorem 6, a characterization of graphic theta-orderable matroids.
Proof of Theorem 6. It is clear that a graphic matroid is theta-orderable. Moreover, Wagner [9] proved that a matroid is graphic if and only if it has no set of incompatible arcs. Now suppose that M has a circuit C and a set {A 1 , A 2 , A 3 } of incompatible arcs of C. It remains to show that M is not theta-orderable. Our proof of this is a straightforward modification of Wagner's proof that no graphic matroid has a set of incompatible arcs [9, Lemma 2]. Assume that M is theta-orderable. Because each of A 1 , A 2 , and A 3 is an arc, for each i in {1, 2, 3}, there is a theta-graph of M in which A i is a theta-arc. As M is theta-orderable, A i is a block in a consistent ordering of M. As {A 1 , A 2 , A 3 } is an incompatible set, there are distinct elements e 1 , e 2 , and e 3 of C such that e ∈ A 1 ∩ A 2 ∩ A 3 and e i ∈ A i − (A j ∪ A k ) for all {i, j, k} = {1, 2, 3}. For each h in {2, 3}, the set A 1 ∪ A h is a block in C in which e appears between e 1 and e h . Then e does not appear between e 2 and e 3 in A 2 ∪ A 3 , a contradiction.
To prove Theorem 7, we will establish the following equivalent version of it.

Theorem 39. A simple connected non-binary matroid is theta-orderable if and only if it
is a balanced series extension of U 2,n for some n 4.
Proof. First, for n 4, the matroid U 2,n and its series extensions have no theta-graphs. Therefore, consistent orderings of these matroids are also theta-orderings. Conversely, suppose M is a simple connected non-binary orderable matroid. By Theorem 37 and Lemma 36, for some n 4, we can obtain M from a balanced series extension B of U 2,n by a sequence of parallel-path additions. It now suffices to show that the sequence of parallel-path additions is empty.
Suppose to the contrary that P ′ is a set added in parallel to a subset P of a series class S of B. Note |P | 2 since M is simple. Now, by Proposition 22, each S-block in a consistent ordering of B contains a single element. As B is a restriction of M, this implies that the elements of P are not a block in a consistent ordering of M. Since M has a theta-graph with P and P ′ as theta-arcs, this is a contradiction.

Characterizing 3-Connected Orderable Binary Matroids
This section proves the following partial result towards Conjecture 4. Theorem 5 is an immediate consequence of this result.
Theorem 40. A 4-connected binary orderable matroid with no series minor isomorphic to F * 7 is graphic. Our proof will require the next three results, the first of which is due to Seymour [7]. Two elements are opposite in M(K 4 ) if they form a matching in the K 4 . Proof. Let A, B, C, D, X, and Y be the series classes of M, labelled as in Figure 19. Take elements x in X and y in Y , and suppose x and y are adjacent in the given consistent ordering of M.
In the circuit A ∪ X ∪ C ∪ Y , we have that y is adjacent to at most one member of C. Therefore, in B ∪C ∪Y , there must be an element, b y , of B that is adjacent to y. Similarly, in A ∪ X ∪ B, there must be an element, b x , of B adjacent to x. Now, in B ∪ X ∪ D ∪ Y , we have the block b x xyb y , so no member of D is adjacent to y. By symmetry, no member of A is adjacent to y. Since y is adjacent to at most one element in Y , it follows that there is no second element of A ∪ D ∪ Y adjacent to y, a contradiction. We now prove the main result of this section.
Proof of Theorem 40. Let M be a 4-connected binary orderable matroid that does not have F * 7 as a series minor. Take a consistent ordering of M and assume M is not graphic. Suppose M is cographic, letting M = M * (G) for some graph G. Take an edge e of G with endpoints u and v. Let (x 1 x 2 · · · x n e) be the ordering on the edges meeting u, and let (e y 1 y 2 · · · y m ) be the ordering on the edges meeting v. Then we may assume the ordering on the bond that is the symmetric difference of these two vertex bonds is (x 1 x 2 · · · x n y 1 y 2 · · · y m ), so x n and y 1 are adjacent. Combining Lemma 43 and Theorem 41, we now have that x n and y 1 share an endpoint in G. Hence, {e, x n , y 1 } is a triangle in G, a contradiction as M is 4-connected.
We may now assume that M is not cographic. Let e and f be adjacent elements of M. By Theorem 41, e and f appear as opposite elements in some M(K 4 )-minor of M. Lemma 43 now gives a contradiction.